By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

ISBN-10: 3319139053

ISBN-13: 9783319139050

This monograph is predicated at the 3rd author's lectures on laptop structure, given in the summertime semester 2013 at Saarland college, Germany. It features a gate point development of a multi-core desktop with pipelined MIPS processor cores and a sequentially constant shared memory.

The ebook comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache dependent sequentially constant shared reminiscence. This opens tips to the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and therefore deterministic. by contrast the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness evidence of the shared reminiscence on the gate point are the most technical contributions of this work.

Show description

Read Online or Download A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof PDF

Best compilers books

Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo's Transactions on high-performance embedded architectures and PDF

Transactions on HiPEAC goals on the well timed dissemination of analysis contributions in laptop structure and compilation tools for high-performance embedded computers. spotting the convergence of embedded and general-purpose computers, this magazine publishes unique learn on structures specific at particular computing projects in addition to platforms with extensive software bases.

Get Smart Card Application Development Using Java PDF

In state-of-the-art global, clever playing cards play an more and more very important function in way of life. We stumble upon them as charge cards, loyalty playing cards, digital handbags, overall healthiness playing cards, and as safe tokens for authentication or electronic signature. Their small measurement and the compatibility in their shape with the magnetic stripe card lead them to the perfect vendors of non-public info equivalent to mystery keys, passwords, customization profiles, and scientific emergency info.

A Pipelined Multi-core MIPS Machine Hardware Implementation - download pdf or read online

This monograph is predicated at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland collage, Germany. It incorporates a gate point building of a multi-core desktop with pipelined MIPS processor cores and a sequentially constant shared reminiscence. The publication includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence.

Additional resources for A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof

Example text

We conclude stable(y, c + 1), which shows part 2 for c + 1. Since all input and clock enable signals for register x[i] are stable at clock edge c + 1, we get from the register semantics of the detailed model for all t ∈ [e(c + 1) + σ, e(c + 2) + ρ]: x[i](t) = x[i]in(e(c + 1)) x[i]ce(e(c + 1)) = 1 x[i](e(c + 1)) x[i]ce(e(c + 1)) = 0. Observing that for all y we have e(c + 1) ∈ [e(c) + tmax(y), e(c + 1) + tmin(y)] , we conclude with part 1 of the induction hypothesis: x[i](e(c + 1)) = x[i]c x[i]in(e(c + 1)) = x[i]inc x[i]ce(e(c + 1)) = x[i]cec .

If there are no malfunctions where one would worry about them in view of later insights, one looks for explanations. It turned out that the hardware engineer who transferred the design to the FPGA had made a single change to the design (without telling anybody about it): he had put a register stage in front of the main memory. In the physical design, this register served as interface circuitry to the main memory and happened to conform to all conditions presented in Sect. 5. Thus, although the digital portion of the processor was completely verified, the design in the book still contained a bug, which is only visible in the detailed model.

Proof. By contradiction. Assume a path s[0 : k] with k > #G exists in the circuit. All si are gates except possibly s0 which might be an input. Thus, a gate must be (at least) twice on the path: ∃i, j : i < j ∧ si = sj . Then s[i : j] is a cycle3 . 3 This proof uses the so called pigeonhole principle. If k + 1 pigeons are sitting in k holes, then one hole must have at least two pigeons. 2 Some Basic Circuits 33 Since every path in a circuit has finite length, one can define for each signal s the depth d(s) of s as the number of gates on a longest path from an input to s: d(s) = max{m | ∃ path s[0 : m] : s0 ∈ In ∧ sm = s} .

Download PDF sample

A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul


by Brian
4.5

Rated 4.46 of 5 – based on 9 votes