By Tetsuya Sato, Hitoshi Murai (auth.), Amos Omondi, Stanislav Sedukhin (eds.)

ISBN-10: 354020122X

ISBN-13: 9783540201229

ISBN-10: 3540398643

ISBN-13: 9783540398646

This convention marked the ?rst time that the Asia-Paci?c desktops structure convention was once held open air Australasia (i. e. Australia and New Zealand), and was once, we are hoping, the beginning of what is going to be a customary occasion. The convention begun in 1992 as a workshop for laptop architects in Australia and in this case built right into a full-?edged convention protecting Austra- sia. extra significant adjustments resulted in the current convention. The ?rst was once a metamorphosis from “computer structure” to “computer structures architecture”, a metamorphosis that famous the significance and shut courting to desktop arc- tecture of yes degrees of software program (e. g. working platforms and compilers) and of different components (e. g. laptop networks). the second one switch, which re?ected the expanding variety of papers being submitted from Asia, was once the alternative of “Australasia” with “Asia-Paci?c”. This year’s occasion used to be hence rather signi?cant, in that it marked the start of a very “Asia-Paci?c” convention. it truly is meant that during the long run the convention venue will exchange among Asia and Australia/New Zealand and, even though nonetheless small, we are hoping that during time the convention will turn into a massive person who represents Asia to an analogous - tent as latest significant computer-architecture meetings in North the United States and Europe symbolize these regions.

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The S-base, LCQ slot number and processor id of the producer thread are then determined from this table for each consumer thread using its sequence number minus dep, and the producer’s S-base is copied and becomes the consumer’s D-base. Note that the processor id and LCQ slot number of the producer thread are required by the consumer thread’s LCQ to signal the producer’s LCQ when it has been killed, as only then can the producer thread’s shared resources be released. If we assume that each LCQ has 64 slots, enough to have one thread waiting in each of the CMP’s 512 registers, then keeping track of dependencies requires another 13 bits of storage per register and again is linear in the number registers in the CMP.

In fact there is just one issue and that is in providing support for concurrency within the ISA. More and more gates mean increased on-chip concurrency, first in word width, now in instruction issue width. The move to a RISC ISA was revolutionary, it did not introduce concurrency explicitly, rather it introduced a simple, regular instruction set that facilitated efficient instruction execution using pipelines. In fact many people forget that the simplicity of RISC was first adopted in order to squeeze a full 32-bit microprocessor onto a single chip for the first time.

1 Out-of-Order Instruction Execution Out-of-order instruction execution can be seen as a theoretically optimal solution for exploiting ILP concurrency, because instructions are interleaved in the wide-issue Multi-threaded Microprocessors – Evolution or Revolution 23 pipelines in close to programmed order, whilst honouring any data and control dependencies or indeed any storage conflicts introduced by the out-of-order instruction execution. The major benefit is that it is achieved using the existing sequential instruction stream and therefore maintains code-base compatibility.

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Advances in Computer Systems Architecture: 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003. Proceedings by Tetsuya Sato, Hitoshi Murai (auth.), Amos Omondi, Stanislav Sedukhin (eds.)

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